I recently graduated with a Master's degree in Software Engineering from SCS of Carnegie Mellon University and will join AWS in Bellevue as a Software Development Engineer in June 2025. Before that, I obtained my Bachelor's degree in Software Engineering from Tongji University. During my Bachelor degree, I interned at Shanghai AI Lab and ByteDance AI Lab.
My background in software engineering has provided me with strong engineering skills. Based on this foundation, my primary experiences and interests include but are not limited to:
You could also refer to the projects page for details. Additionally, I am currently keen to explore the fields of LLMs and MLSys.
I am actively seeking a PhD position for Fall 2026. I am also open to discussing a wide range of interesting topics, including but not limited to potential collaboration opportunities. Please feel free to reach out if you'd like to have a chat!
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Anjiang Wei, Huanmi Tan, Tarun Suresh, Daniel Mendoza, Thiago SFX Teixeira, Ke Wang, Caroline Trippel, Alex Aiken
arXiv preprint Under review. 2025
VeriCoder is a model for RTL (Register Transfer Level) code generation, fine-tuned on a novel dataset that is functionally validated via feedback-directed refinement. Unlike prior datasets that only ensure syntactic correctness, our dataset guarantees that each RTL design passes automatically generated unit tests aligned with its natural language specification. Our key contributions include: (1) a large-scale dataset of 125,000+ examples with simulation-passing RTL designs, (2) a feedback-driven construction methodology that iteratively refines designs and tests based on test results, (3) superior performance with up to +71.7% relative improvement on VerilogEval benchmarks, and (4) comprehensive resources including dataset, model weights, inference scripts, and training pipeline.
Anjiang Wei, Huanmi Tan, Tarun Suresh, Daniel Mendoza, Thiago SFX Teixeira, Ke Wang, Caroline Trippel, Alex Aiken
arXiv preprint Under review. 2025
VeriCoder is a model for RTL (Register Transfer Level) code generation, fine-tuned on a novel dataset that is functionally validated via feedback-directed refinement. Unlike prior datasets that only ensure syntactic correctness, our dataset guarantees that each RTL design passes automatically generated unit tests aligned with its natural language specification. Our key contributions include: (1) a large-scale dataset of 125,000+ examples with simulation-passing RTL designs, (2) a feedback-driven construction methodology that iteratively refines designs and tests based on test results, (3) superior performance with up to +71.7% relative improvement on VerilogEval benchmarks, and (4) comprehensive resources including dataset, model weights, inference scripts, and training pipeline.